This invention relates to digital data communications systems and more particularly to phase-locked loops (PLLs) for extraction of a bit clock from digital data.
Digital techniques are commonly used for low-cost, low-quality PLLs. Digital techniques are also attractive for high-quality PLLs because these techniques permit precise, no-drift, no-offset, no-adjustment operation except for the reference signal generator. It has been considered difficult, however, to employ digital techniques for PLLs operating at frequencies close to or exceeding the maximum speeds of the logic circuitry. The source of this difficultly is that digital PLLs typcially employ a reference signal generator and a divide-by-N counter controlled by a phase slip rate control signal. The phase of the counter is made to slip by one cycle of the reference frequency in order to move the phase of the output frequency by 1/N cycle. The phase slip rate control signal controls the output frequency and the output signal is approximately smooth or phase-continuous to the degree that N is large. This forces the maximum logic speed to be N times the output rate.
One alternative is to use a digitally-controlled low frequency with a high reference frequency. But the large difference between these frequencies leads to relatively close sum and difference frequencies from the mixer, requiring a high-quality filter to separate them, a major economic setback.
It might appear that a simple slave PLL multiplying the digitally-controlled low frequency up to the required output frequency might offer a solution. But any frequency multiplier will also multiply the size of the phase slips measured in degrees or cycles.